FPGA Design Engineer

Expected, Verilog, SystemVerilog, SoC, ARM CSS, DDR4/DDR5, PCIe Gen5, Gen4 IPOptional, Design Compiler, SpyGlass CDC/DFT, Fusion Compiler, Python, TCL, Linux, firmwareOperating system, LinuxAbout the project, We’re building a next-generation high-performance SoC platform targeting cloud and AI workloads. Join us as a Digital Design Engineer to design cutting-edge digital blocks, including multi-core ARM Cortex subsystems (ARM CSS), DDR5 memory controllers, PCIe Gen5 interfaces, and advanced SoC…